voice eletech electronics, inc. 16019 kaplan avenue industry, ca 91744, u.s.a. tel: (626) 333-6394 fax: (626) 333-6494 eletech enterprise co., ltd. 531-3f chung-cheng road hsin tien, taipei hsien, taiwan tel:+886 2-2218-0068 fax:+886 2-2218-0254 http://www.eletech.com features n high quality voice & sound generation n record & playback with external sram n playback-only with external eprom or rom n stand-alone operation n 32k x 8 direct memory addressing, expandable n single 5v dc supply voltage general descriptions the VP-1000A is an advanced cmos lsi chip for general purpose voice/sound record and playback applications. it can be interfaced with external sram to construct a realtime recording circuitry, or with external rom or eprom for playback only applications. when rom or eprom is used, the sound must be digitized by using eletech's vp-880 voice development system or vw- 1000a voice eprom writer. applications n voice memo recorder n sound effects generator VP-1000A digital voice processor VP-1000A (dip40) pin assignment VP-1000Af (qfp48) pin assignment n low power consumption n continuous variable slope delta (cvsd) modulation n sampling rate from 24kbps to 128 kbps n message digitization with the vp-880 or the vw-1000a n pin to pin compatible with um5100 n 40-pin dip (VP-1000A) or 48-pin qfp (VP-1000Af) the VP-1000A is totally self-contained. it can access the external memory all by itself without the help from any microprocessor. although the chip provides only 15 address lines, an external counter can be easily added to extend the memory addressing to virtuely no limitation. therefore very long message length can be achieved easily. overall, the VP-1000A offers high voice quality and flexible memory addressing that no other chips can. n digital announcer for consumer, industrial, security and telecommunication products
absolute maximum ratings* supply voltage, v dd - v ss ..................................... 0 to 5.5v input volotage, v in ........................................... v ss to v dd operating temperature, t op ...................... -10 o c to 60 o c storage temperature, t st .......................... -20 o c to 80 o c * stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. electrical characteristics (v dd = 5v, f osc = 64khz, f clock = 32 khz unless otherwise specified) symbol parameter min. typ. max. units v dd supply voltage 4.5 5 5.5 v i dd standby current 50 ua i drive clock drive current 16 ma i sink clock sink current 16 ma v ih input high 3.5 5 v v il voltage low 0 1.5 v i drive output drive 3 4 ma i sink current sink 3 4 ma t reset reset pulse width 500 ns t write write pulse width 200 ns s/n signal-to-quantizied noise ratio 30 db timing diagram VP-1000A ..........................................................................................2 voice c1 clk (internal) record r/w reset play read a0 a1
VP-1000A ..........................................................................................3 voice pin descriptions a0 - a14 output, address bus, expandable by adding a counter. ang & ang output, differential analog audio signal. c1 input, internal rc oscillator. if external clock is to be used, it must be connected to this pin and its frequency twice as fast as the sampling rate. clk drv output, a square wave of the same frequency as the sampling rate when the chip is in the record or the play mode. the frequency will be lower when the chip is in the idle mode. compdata input, feedback from the external comparator output. d0 - d7 input/output, data bus. env input, to be connected to an external integrator output. int output, connected to an external integrator to produce envelope waveform. gnd ground. play input, active low. when the chip is idle but not under reset, pulsing this pin will put the chip in the play mode. r1 output, internal rc oscillator. leave un-connected when using external clock. read output, active low. it indicates the chip is in the play mode. this signal is usually used to enable memory output. record input, active low. when the chip is idle but not under reset, pulsing this pin will put the chip in the record mode. reset input, active high. reset the chip back to the idle mode. this pin is level sensitive. r/w output, active low. this pin generates a pulse each time the clock counts to eight. it is usually used as a write strobe for the sram. active only in the record mode. td, td output, for signal modulation. these pins are useful in the record mode only. vdd input, supply voltage. addr ess generator osc. & timing ctrl output buffer (tri-state) 8-bit shift register a0 : a14 r1 c1 clk drv d0 ..............d7 record play read r/w ang ang compdat a reset td td env int modulator mo de control vdd gnd block diagram
VP-1000A ..........................................................................................4 voice application notes 1. reset consideration the reset pin should never be left floating. if the reset pin is not con- trolled by a non-floating signal, use the following reset circuitry. note that the 0.01uf capacitor is added so that the VP-1000A gets a reset pulse on power-up. 2. memory address expansion the VP-1000A's internal 15-bit address counter covers memory space up to 32k x 8, or 256k bits. it can be easily expanded by just adding a binary counter, clocked by the falling edge of address line a14. the first counter output becomes a15, the second output becomes a16 and etc. this is possible since once started, the VP-1000A will not stop recording or playing until it is reset. when the internal counter reaches the maximum count, it simply overflows and restarts from zero again. therefore the vp- 1000a can access an unlimited amount of memory. circuit design examples 1. single-message record and play, 1m sram
VP-1000A ..........................................................................................5 voice 3. multiple-message playback, sequential control the 8m eprom is divided into 32 equal segments of 256k bits. each message is stored in such a segment and must be 256k bits or smaller. the first trigger will activate only the first segment. the next trigger will activate the next segment, and etc. 4. multiple-message playback, controller interface the 8m eprom is divided into 32 equal segments of 256k bits. each message is stored in such a segment and must be 256k bits or smaller. the message is activated via a controller interface which consists of 5 address lines and a strobe signal (play). 2. single-message playback, 8m eprom
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